Intellectual Property India Publishes Patent Application for A System And Method For Runtime Bypass Of Aging Interconnect Segments In A Network-On-Chip Using A Graph Neural Network

MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202621100406 A) filed by Prof. Mahendra S. Dalvi; Prof. Snehal H. Gorde; Prof. Ujjwala D. Deore; Prof. Aarti D. Nimse; Prof. Kavita Y. Sonawane; and Prof. Rita G. Patil on August 19, 2026, for A System And Method For Runtime Bypass Of Aging Interconnect Segments In A Network-On-Chip Using A Graph Neural Network.

Inventors include Prof. Mahendra S. Dalvi; Prof. Snehal H. Gorde; Prof. Ujjwala D. Deore; Prof. Aarti D. Nimse; Prof. Kavita Y. Sonawane; and Prof. Rita G. Patil.

The application for the patent was published on October 02, 2026, under issue no. 40/2026.

Abstract: [064] The present invention provides a system and method for runtime bypass of a...