Intellectual Property India Publishes Patent Application for A System And Method For A Microchip Layout Architecture For Low-Power Edge Computing Devices

MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202621058503 A) filed by Dr. Sheetal Bawane; Mr. Gaurav Matange; Dr. Swati Dhondiram Jadhav; Dr. Ooi Chee Pun; Dr. Tan Wooi Haw; Dr. Tan Yi Fei; Dr. Anurag Shrivastava; and Ravi Kalra on May 07, 2026, for A System And Method For A Microchip Layout Architecture For Low-Power Edge Computing Devices.

Inventors include Dr. Sheetal Bawane; Mr. Gaurav Matange; Dr. Swati Dhondiram Jadhav; Dr. Ooi Chee Pun; Dr. Tan Wooi Haw; Dr. Tan Yi Fei; Dr. Anurag Shrivastava; and Ravi Kalra.

The application for the patent was published on July 10, 2026, under issue no. 28/2026.

Abstract: The present invention relates to a microchip layout architecture for edge computin...