Intellectual Property India Publishes Patent Application for A Low-Power Dynamic Cmos Comparator With Integrated Leakage Control Techniques For High-Speed Applications

MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641115569 A) filed by Vallurupalli Nageswara Rao Vignana Jyothi Institute Of Engineering And Technology on September 26, 2026, for A Low-Power Dynamic Cmos Comparator With Integrated Leakage Control Techniques For High-Speed Applications.

Inventor includes Dr. K L V Ramana Kumari.

The application for the patent was published on October 02, 2026, under issue no. 40/2026.

Abstract: ABSTRACT [0027] This invention introduces a low-power dynamic CMOS comparator designed using 22nm and 45nm technology, operating at varying voltages. We employ circuit-level techniques such as ONOFIC (On-Off logic circuit), LCNT (Leakage Control NMOS transistor), and LCMT...