Intellectual Property India Publishes Patent Application for A Hybrid Geometric-Boolean Digital Logic Architecture And Canonical Decomposition Engine For Low-Power, High-Speed Computing

MUMBAI, India, July 30 -- Intellectual Property India has published a patent application (202641085139 A) filed by Pradeep K B; Praseetha K B; Nisha K B; and Smitha K B on July 11, 2026, for A Hybrid Geometric-Boolean Digital Logic Architecture And Canonical Decomposition Engine For Low-Power, High-Speed Computing.

Inventors include Pradeep K B; Praseetha K B; Nisha K B; and Smitha K B.

The application for the patent was published on July 24, 2026, under issue no. 30/2026.

Abstract: A Hybrid Geometric-Boolean Digital Logic Architecture and Canonical Decomposition Engine for low-power, high-speed computing. The Architecture partitions an N- bit input vector into a higher-order bit field and a lower-order bit field at a Primitive Boundary ...