Intellectual Property India Publishes Patent Application for A High-Speed Error Correction Architecture For Data Transmission

MUMBAI, India, July 24 -- Intellectual Property India has published a patent application (202611063572 A) filed by Noida Institute Of Engineering & Technology on May 20, 2026, for A High-Speed Error Correction Architecture For Data Transmission.

Inventors include Dr. Sarabjeet Kaur; and Dr. Prachi Tripathi.

The application for the patent was published on July 17, 2026, under issue no. 29/2026.

Abstract: A high-speed error correction architecture for data transmission is disclosed. The architecture includes an input framing interface, a segment distributor, a parallel syndrome computation engine, an adaptive error pattern classifier, a correction mask generator, a pipelined data alignment buffer, a reliability evaluator, a configuration a...