MUMBAI, India, Nov. 6 -- Intellectual Property India has published a patent application (202641131772 A) filed by Dayananda Sagar College Of Engineering on November 04, 2026, for A Flyback Converter System With Active Disturbance Rejection Control For Reduced Output Capacitance.
Inventors include Dr. Priyanshu Kumar; Devaraj; Bharat Sai; Kashyap Hande P; Kevin David; Dr. Anubhav Kumar Pandey; and Dr. G Manikanta.
The application for the patent was published on November 06, 2026, under issue no. 45/2026.
Abstract: The present invention discloses a flyback converter system employing an Active Disturbance Rejection Control (ADRC)-based control scheme for regulating output voltage under variable operating conditions. The system incorporates ...