Intellectual Property India Publishes Patent Application for A Design Of A Low-Power Spi Master Controller Utilizing Dynamic Power-Gating And Upf-Driven Physical Synthesis

MUMBAI, India, Nov. 13 -- Intellectual Property India has published a patent application (202641123497 A) filed by K. S. Rangasamy College Of Technology on October 15, 2026, for A Design Of A Low-Power Spi Master Controller Utilizing Dynamic Power-Gating And Upf-Driven Physical Synthesis.

Inventors include Dr. S. Pradeep; Mr. T. Rajavenkatesan; Mr. S. Saravanan; Mr. Poovarasan R; Mr. S. R. Kousik Kumar; and Ms. A. Sathurthiga.

The application for the patent was published on November 13, 2026, under issue no. 46/2026.

Abstract: A low-power Serial Peripheral Interface (SPI) master controller utilizing dynamic power-gating and Unified Power Format (UPF)-driven physical implementation is disclosed herein. The controller comprises an SPI cont...