Intellectual Property India Publishes Patent Application for 'Design And Implementation Of A Modified Carry Select Adder On Cyclone III FPGA' Filed by Srinivasa Ramanujan Institute Of Technology; Dr. K. Dadasikandar; J. Haritha; U. Pavitra; and K. Balaji

MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202641050118 A) filed by Srinivasa Ramanujan Institute Of Technology; Dr. K. Dadasikandar; J. Haritha; U. Pavitra; and K. Balaji, Ananthapuramu, Andhra Pradesh, on April 20, for 'design and implementation of a modified carry select adder on cyclone iii fpga.'

Inventor(s) include Srinivasa Ramanujan Institute Technology; Dr. K. Dadasikandar; J. Haritha; U. Pavitra; and K. Balaji.

The application for the patent was published on May 1, under issue no. 18/2026.

According to the abstract released by the Intellectual Property India: "In modern digital systems, arithmetic operations play a crucial role in determining overall performance, especially in Digita...