India, June 22 -- The rapid growth of demand for AI semiconductors is driving the evolution of advanced packaging technologies, with Fan-Out Panel-Level Packaging (FOPLP) emerging as a new battleground across the industry.

TrendForce reports that TSMC is currently focusing on its Chip-on-Panel-on-Substrate (CoPoS) packaging architecture and has standardized on a 310 x 310 mm panel format.

The year 2026 is expected to serve as a critical validation period for related equipment and materials suppliers, with pilot production targeted for 2027 and mass production slated for the second half of 2028. Beyond CoPoS, TSMC's next major focus is expected to shift toward glass core substrates, with commercial-scale production likely to occur after ...