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US Patent Issued to VERIFAI on May 12 for "Method and system for using deep learning to improve design verification by optimizing code coverage, functional coverage, and bug detection" (California, New Jersey Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,626,041, issued on May 12, was assigned to VERIFAI INC. (Palo Alto, Calif.). "Method and system for using deep learning to improve design verifi... Read More


US Patent Issued to RISCURE BEHEER on May 12 for "Side channel leakage source identification in an electronic circuit design" (American, Dutch Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,626,042, issued on May 12, was assigned to RISCURE BEHEER B.V. (Delft, Netherlands). "Side channel leakage source identification in an electroni... Read More


US Patent Issued to Synopsys on May 12 for "Automatic test pattern generation to increase coverage in detecting defects in analog circuits" (California Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,626,043, issued on May 12, was assigned to Synopsys Inc. (Sunnyvale, Calif.). "Automatic test pattern generation to increase coverage in detecti... Read More


US Patent Issued to Cadence Design Systems on May 12 for "Creating netlists from distributed interactive applications" (French Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,626,044, issued on May 12, was assigned to Cadence Design Systems Inc. (San Jose, Calif.). "Creating netlists from distributed interactive appli... Read More


US Patent Issued to International Business Machines on May 12 for "Cell-based signal connectivity between wafer frontside and backside" (New York Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,626,045, issued on May 12, was assigned to International Business Machines Corp. (Armonk, N.Y.). "Cell-based signal connectivity between wafer f... Read More


US Patent Issued to D2S on May 12 for "Generating routes for an integrated circuit design with non-preferred direction curvilinear wiring" (California Inventor)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,626,046, issued on May 12, was assigned to D2S INC. (San Jose, Calif.). "Generating routes for an integrated circuit design with non-preferred d... Read More


US Patent Issued to D2S on May 12 for "Computing and displaying a predicted overlap shape in an IC design based on predicted misalignment of metal layers" (California Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,626,047, issued on May 12, was assigned to D2S INC. (San Jose, Calif.). "Computing and displaying a predicted overlap shape in an IC design base... Read More


US Patent Issued to CANVA on May 12 for "Systems and methods for processing designs" (Australian Inventor)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,626,048, issued on May 12, was assigned to CANVA PTY LTD (Surry Hills, Australia). "Systems and methods for processing designs" was invented by ... Read More


US Patent Issued to discourse.ai on May 12 for "System and method for automatic summarization in interlocutor turn-based electronic conversational flow" (British, American, Portuguese Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,626,049, issued on May 12, was assigned to discourse.ai Inc. (Dallas). "System and method for automatic summarization in interlocutor turn-based... Read More


US Patent Issued to GOOGLE on May 12 for "Semi-autoregressive text editing" (Swiss Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,626,050, issued on May 12, was assigned to GOOGLE LLC (Mountain View, Calif.). "Semi-autoregressive text editing" was invented by Jonathan Steph... Read More