US Patent Issued to XILINX on July 14 for "Lock and buffer scheduling in multi-core architectures" (Indian Inventor)

ALEXANDRIA, Va., July 14 -- United States Patent no. 12,681,776, issued on July 14, was assigned to XILINX INC. (San Jose, Calif.).

"Lock and buffer scheduling in multi-core architectures" was invented by Ajit Kumar Agarwal (Hyderabad, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "Application code is compiled to generate code to be executed by the cores of a multi-core architecture. Generating the code includes mapping kernels of the application onto the DPEs, and generating main code for cores of the DPEs. The main code is generated by initializing locks for each kernel associated with the cores the DPEs. The locks are associated with input ports and output ports of the kernels. Further, buffers are ...