US Patent Issued to Tokyo Electron on Dec. 23 for "3D advanced transistor architecture integrated with source/drain spider design" (New York Inventors)

ALEXANDRIA, Va., Dec. 23 -- United States Patent no. 12,507,447, issued on Dec. 23, was assigned to Tokyo Electron Ltd. (Tokyo).

"3D advanced transistor architecture integrated with source/drain spider design" was invented by H. Jim Fulford (Albany, N.Y.), Mark I. Gardner (Albany, N.Y.) and Partha Mukhopadhyay (Albany, N.Y.).

According to the abstract* released by the U.S. Patent & Trademark Office: "One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a source contact, a drain contact, a 2D material forming a channel between the source and drain contacts and surrounding a carrier nanosheet forming a first p-n ju...