US Patent Issued to The Regents of the University of California on Sept. 29 for "Reliable and fault-tolerant clock generation and distribution for chiplet-based waferscale processors" (California Inventors)

ALEXANDRIA, Va., Sept. 30 -- United States Patent no. 12,748,454, issued on Sept. 29, was assigned to The Regents of the University of California (Oakland, Calif.).

"Reliable and fault-tolerant clock generation and distribution for chiplet-based waferscale processors" was invented by Puneet Gupta (Los Angeles) and Saptadeep Pal (Los Angeles).

According to the abstract* released by the U.S. Patent & Trademark Office: "The present embodiments provide a solution for clock delivery, distribution to an entire waferscale system composed of many chiplets. A clock distribution scheme according to embodiments is also fault tolerant, i.e., the clock distribution network can avoid faulty chiplets on the substrate and reliably distribute clock to all...