US Patent Issued to Synopsys on Sept. 29 for "Error-correcting and error-detecting parity-check matrix to store a known bad data bit in a memory system" (Indian Inventors)

ALEXANDRIA, Va., Sept. 30 -- United States Patent no. 12,748,660, issued on Sept. 29, was assigned to Synopsys Inc. (Sunnyvale, Calif.).

"Error-correcting and error-detecting parity-check matrix to store a known bad data bit in a memory system" was invented by Abhishek Kumar Shivakumar (Pathanamthitta, India) and Biswanath Tayenjam (Bangalore, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "A system includes: an error correction code (ECC) memory controller configured to read data stored in a memory, the data including a read codeword including system data and parity data, the ECC memory controller including an ECC decoder configured to: compute a syndrome based on the read codeword using a parity-check...