US Patent Issued to Synopsys on June 2 for "Creation of reduced formal model for scalable system-on-chip (SoC) level connectivity verification" (American, Indian Inventors)

ALEXANDRIA, Va., June 2 -- United States Patent no. 12,645,856, issued on June 2, was assigned to Synopsys Inc. (Sunnyvale, Calif.).

"Creation of reduced formal model for scalable system-on-chip (SoC) level connectivity verification" was invented by Prasun Das (Bangalore, India), Pratik Mahajan (Santa Clara, Calif.), Alfred Koelbl (Mosier, Ore.) and Henna Arora (Howrah, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "A method of verifying connectivity in a circuit design, includes, in part, receiving a netlist of the circuit design; designating a plurality of destination nodes associated with the netlist; for each of the plurality of destination nodes, identifying one or more source nodes that are trave...