US Patent Issued to Synopsys on April 21 for "Logic verification of superconducting electronic circuits, including for margin analysis of yield" (Colorado Inventor)

ALEXANDRIA, Va., April 21 -- United States Patent no. 12,608,524, issued on April 21, was assigned to Synopsys Inc. (Sunnyvale, Calif.).

"Logic verification of superconducting electronic circuits, including for margin analysis of yield" was invented by Aaron John Barker (Broomfield, Colo.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Logic verification of superconducting electronic circuits is implemented as follows. The superconducting electronic circuit is supposed to implement a desired logic function. A description of the circuit includes a plurality of nodes of the circuit, including one or more input nodes and one or more output nodes. Operation of the superconducting electronic circuit is simulated, ...