US Patent Issued to Renesas Electronics on July 21 for "Regulator circuit for accepting range of input voltages while achieving lower power consumption" (Japanese Inventors)

ALEXANDRIA, Va., July 21 -- United States Patent no. 12,687,870, issued on July 21, was assigned to Renesas Electronics Corp. (Tokyo).

"Regulator circuit for accepting range of input voltages while achieving lower power consumption" was invented by Atsushi Tsuda (Tokyo) and Kosuke Yayama (Tokyo).

According to the abstract* released by the U.S. Patent & Trademark Office: "A capless regulator circuit is provided. The regulator circuit includes a power transistor that controls the supply of current to an external output terminal connected to a load; a monitor transistor provided between the external output terminal and a reference voltage terminal to which a reference voltage is supplied, and through which a current corresponding to the volt...