US Patent Issued to Powerchip Semiconductor Manufacturing on Sept. 1 for "Memory tile with probe pad arrangement and stacked memory device" (Japanese Inventor)

ALEXANDRIA, Va., Sept. 1 -- United States Patent no. 12,727,497, issued on Sept. 1, was assigned to Powerchip Semiconductor Manufacturing Corp. (Hsinchu, Taiwan).

"Memory tile with probe pad arrangement and stacked memory device" was invented by Takeo Okamoto (Osaka, Japan).

According to the abstract* released by the U.S. Patent & Trademark Office: "A memory tile with a probe pad arrangement and a stacked memory device are provided. The memory tile has a first and a second surfaces; a first probe pad set, having first probe pads and provided on the first surface; a second probe pad set, having second probe pads and provided on the second surface; first conductive connections, each of which is connected to a corresponding first probe pad; ...