US Patent Issued to Micron Technology on Feb. 17 for "Erase pulse loop dependent adjustment of select gate erase bias voltage" (California, Idaho Inventors)

ALEXANDRIA, Va., Feb. 17 -- United States Patent no. 12,555,638, issued on Feb. 17, was assigned to Micron Technology Inc. (Boise, Idaho).

"Erase pulse loop dependent adjustment of select gate erase bias voltage" was invented by Ching-Huang Lu (Fremont, Calif.), Vinh Quang Diep (Hayward, Calif.), Avinash Rajagiri (Boise, Idaho) and Yingda Dong (Los Altos, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. During a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated...