US Patent Issued to Micron Technology on April 7 for "Selectively erasing one of multiple erase blocks coupled to a same string using gate induced drain leakage" (Singaporean, American, Japanese Inventors)

ALEXANDRIA, Va., April 7 -- United States Patent no. 12,597,472, issued on April 7, was assigned to Micron Technology Inc. (Boise, Idaho).

"Selectively erasing one of multiple erase blocks coupled to a same string using gate induced drain leakage" was invented by Shyam Sunder Raghunathan (Woodlands, Singapore), Yingda Dong (Los Altos, Calif.) and Akira Goda (Tokyo).

According to the abstract* released by the U.S. Patent & Trademark Office: "An apparatus can comprise a memory array comprising a plurality of strings of memory cells. A first string of the plurality of strings can comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupl...