US Patent Issued to Kioxia on July 14 for "Memory system applying read voltage for reading data with small number of fail bits" (Japanese Inventors)

ALEXANDRIA, Va., July 14 -- United States Patent no. 12,682,942, issued on July 14, was assigned to Kioxia Corp. (Tokyo).

"Memory system applying read voltage for reading data with small number of fail bits" was invented by Naomi Takeda (Yokohama Kanagawa, Japan) and Masanobu Shirakawa (Chigasaki Kanagawa, Japan).

According to the abstract* released by the U.S. Patent & Trademark Office: "A memory system includes: a non-volatile memory including blocks each including memory cells; and a memory controller configured to execute a first read process of reading data from a first memory cell in a first block by using a first voltage and a second read process of reading data from a second memory cell in the first block by using a second voltage...