US Patent Issued to Intel on Oct. 20 for "Memory chip with per row activation count having error correction code protection" (California, Washington, South Carolina, Oregon, North Carolina Inventors)

ALEXANDRIA, Va., Oct. 21 -- United States Patent no. 12,769,612, issued on Oct. 20, was assigned to Intel Corp. (Santa Clara, Calif.).

"Memory chip with per row activation count having error correction code protection" was invented by Bill Nale (Livermore, Calif.), Kuljit S. Bains (Olympia, Wash.), Lawrence D. Blankenbeckler (Cary, N.C.), Ronald Anderson (Columbia, S.C.) and Jongwon Lee (Portland, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ...