US Patent Issued to Intel on May 5 for "Approach to prevent plating at v-groove zone in photonics silicon during bumping or pillaring" (Arizona Inventor)

ALEXANDRIA, Va., May 5 -- United States Patent no. 12,619,038, issued on May 5, was assigned to Intel Corp. (Santa Clara, Calif.).

"Approach to prevent plating at v-groove zone in photonics silicon during bumping or pillaring" was invented by Santosh Shaw (Chandler, Ariz.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Embodiments disclosed herein include electronic devices and methods of forming electronic devices. In an embodiment, an electronic device comprises a die. In an embodiment, the die comprises a semiconductor substrate, a bump field over the semiconductor substrate, and a V-groove into the semiconductor substrate, wherein the V-groove extends to an edge of the semiconductor substrate. In an embod...