US Patent Issued to INTEL NDTM US on Sept. 8 for "Barrier and thin spacer for 3D-NAND complementary metal-oxide semiconductor under array" (Chinese, American Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,733,169, issued on Sept. 8, was assigned to INTEL NDTM US LLC (Santa Clara, Calif.).

"Barrier and thin spacer for 3D-NAND complementary metal-oxide semiconductor under array" was invented by Yi Zhang (Da Lian, China), Hongxiang Mo (Da Lian, China) and Tony Zengtao Liu (Eagle, Idaho).

According to the abstract* released by the U.S. Patent & Trademark Office: "Systems, apparatuses, and methods may provide for technology for forming a gate polysilicon for 3D-NAND complementary metal-oxide semiconductor under array (CuA) on a substrate with a barrier and spacer structure. For example, the technology includes forming a titanium nitride (TiN) barrier adjacent the gate polysilicon and formi...