US Patent Issued to Cadence Design Systems on Sept. 9 for "Efficient clocking structures for high-speed systems using hybrid digital delay lanes" (Indian Inventors)

ALEXANDRIA, Va., Sept. 10 -- United States Patent no. 12,413,213, issued on Sept. 9, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"Efficient clocking structures for high-speed systems using hybrid digital delay lanes" was invented by Jitendra Kumar Yadav (Bengaluru, India), Sachin Ramesh Gugwad (Karnataka, India), Hari Anand Ravi (Karnataka, India) and Hajee Mohammed Shuaeb Fazeel (Bengaluru, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "A high-speed clocking circuit may include a single path digitally controlled coarse delay line including multiple stages. Each of the multiple stages may include a plurality of inverters and a logic gate electrically connected in series that are con...