US Patent Issued to Cadence Design Systems on Sept. 8 for "Voltage regulator improving power supply rejection ratio using a high gain loop" (Indian Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,730,466, issued on Sept. 8, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"Voltage regulator improving power supply rejection ratio using a high gain loop" was invented by Prakash Kumar Lenka (Orissa, India), Harsh Anil Shakrani (Maharashtra, India), Hari Anand Ravi (Bangalore, India), Sachin Ramesh Gugwad (Bangalore, India) and Vinod Kumar (Uttar Pradesh, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "Embodiments included herein are directed towards a voltage regulator circuit. The circuit may include a first stage amplifier circuitry and high gain loop connection circuitry electrically connected with the first stage amplifier c...