US Patent Issued to Cadence Design Systems on May 20 for "Low jitter clock multiplier circuit and method with arbitrary frequency acquisition" (Canadian Inventors)

ALEXANDRIA, Va., June 16 -- United States Patent no. 12,308,850, issued on May 20, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"Low jitter clock multiplier circuit and method with arbitrary frequency acquisition" was invented by Hemesh Yasotharan (Toronto), Navid Yaghini (Pickering, Canada), Zhuobin Li (Markham, Canada), Clifford Ting (Toronto) and Robert Wang (Toronto).

According to the abstract* released by the U.S. Patent & Trademark Office: "A circuit and method are described for generating a low jitter output clock having an arbitrary non-integer divide ratio relative to a high-frequency clock. Integer divide ratios of the high-frequency clock may be achieved by dividing the high-frequency clock by the reference c...