US Patent Issued to Cadence Design Systems on June 2 for "Sampler circuit with low deadband across process, voltage, and temperature" (Indian, American Inventors)

ALEXANDRIA, Va., June 2 -- United States Patent no. 12,647,127, issued on June 2, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"Sampler circuit with low deadband across process, voltage, and temperature" was invented by Hajee Mohammed Shuaeb Fazeel (Bengaluru, India), Vinod Kumar (Uttar Pradesh, India) and Thomas Evan Wilson (Laurel, Md.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Embodiments included herein are directed towards a sampler circuit. Embodiments may include a first positive-channel metal oxide semiconductor (PMOS) or negative-channel metal oxide semiconductor (NMOS) transistor that may be operatively connected to a voltage source and a first output node. A cross-coupled PM...