US Patent Issued to Cadence Design Systems on Dec. 2 for "Systems and methods for reducing test point power consumption in a circuit design" (New York, California Inventors)

ALEXANDRIA, Va., Dec. 2 -- United States Patent no. 12,488,176, issued on Dec. 2, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"Systems and methods for reducing test point power consumption in a circuit design" was invented by Jagjot Kaur (Fremont, Calif.) and Vivek Chickermane (Slaterville Springs, N.Y.).

According to the abstract* released by the U.S. Patent & Trademark Office: "The present disclosure relates to reducing power consumption of test point circuit elements of an integrated circuit (IC) design. An ungated input clock for at least one testing point circuit element for the IC design can be identified. The IC design can be updated by coupling a test point clock gating circuit element to a clock gate input nod...