US Patent Issued to ARTERIS on Nov. 3 for "Process for generating physical implementation guidance during the synthesis of a network-on-chip" (French, American Inventors)

ALEXANDRIA, Va., Nov. 3 -- United States Patent no. 12,782,913, issued on Nov. 3, was assigned to ARTERIS INC. (Campbell, Calif.).

"Process for generating physical implementation guidance during the synthesis of a network-on-chip" was invented by Amir Charif (Paris), Xavier Van Ruymbeke (Clamart, France) and Mark William Bales (Livermore, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "System and methods are disclosed for augmenting a synthesized NoC, with data that guides a physical implementation of the NoC topology in a way that coincides with the topology synthesis result and reduces timing violations in the final physical design. The system generates physical implementation guidance, which is duri...