US Patent Issued to Applied Materials on June 16 for "Method of reducing metal gate resistance for next generation NMOS device application" (California Inventors)

ALEXANDRIA, Va., June 16 -- United States Patent no. 12,660,271, issued on June 16, was assigned to Applied Materials Inc. (Santa Clara, Calif.).

"Method of reducing metal gate resistance for next generation NMOS device application" was invented by Srinivas Gandikota (Santa Clara, Calif.), Yixiong Yang (Fremont, Calif.), Yongjing Lin (San Jose, Calif.), Tuerxun Ailihumaer (Santa Clara, Calif.), Tengzhou Ma (San Jose, Calif.), Yuanhua Zheng (Burlingame, Calif.), Zhihui Liu (Sunnyvale, Calif.), Shih Chung Chen (Cupertino, Calif.), Janardhan Devrajan (Santa Clara, Calif.), Yi Xu (San Jose, Calif.), Yu Lei (Belmont, Calif.) and Mandyam Sriram (San Jose, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Metho...