US Patent Issued to Akeana on Feb. 17 for "Processor pipeline for interlocked data transfer operations with variable latency" (California Inventors)

ALEXANDRIA, Va., Feb. 17 -- United States Patent no. 12,554,503, issued on Feb. 17, was assigned to Akeana Inc. (Santa Clara, Calif.).

"Processor pipeline for interlocked data transfer operations with variable latency" was invented by Ricardo Ramirez (Sunnyvale, Calif.), Albert Anthony Martin (Sunnyvale, Calif.), Abhijit Sil (Dublin, Calif.) and Rabin Sugumar (Sunnyvale, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Disclosed embodiments provide techniques for instruction execution with a processor pipeline for data transfer operations. A processor core is accessed. The processor core executes one or more instructions out of order. The processor core supports integer operations and floating-point ope...