US Patent Issued to Adeia Semiconductor on July 28 for "Systems and methods for releveled bump planes for chiplets" (California Inventors)

ALEXANDRIA, Va., July 28 -- United States Patent no. 12,696,816, issued on July 28, was assigned to Adeia Semiconductor Inc. (San Jose, Calif.).

"Systems and methods for releveled bump planes for chiplets" was invented by Javier A. DeLaCruz (San Jose, Calif.), Belgacem Haba (Saratoga, Calif.), Cyprian Emeka Uzoh (San Jose, Calif.), Rajesh Katkar (Milpitas, Calif.) and Ilyas Mohammed (Santa Clara, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bo...