ALEXANDRIA, Va., June 16 -- United States Patent no. 12,306,660, issued on May 20.
"Ultra-low power D flip-flop with reduced clock load" was invented by Sehat Sutardja (Las Vegas).
According to the abstract* released by the U.S. Patent & Trademark Office: "A latch for a flip-flop or other circuit which requires fewer signal inputs than prior latch designs to reduce power consumption. The latch comprises a first transistor set is switching element and is configured to receive clock signals from a clock network and an input signal. A second transistor receives the input signal from the first transistor set and is configured as a first data buffer to create a latch output. A feedback path includes a third transistor set in series with a resi...