INTERNATIONAL PATENT: MICRON TECHNOLOGY, INC. FILES APPLICATION FOR "STACKED DIE SEMICONDUCTOR PACKAGE INCLUDING AN ARRAY OF PILLAR STRUCTURES"

GENEVA, Feb. 4 -- MICRON TECHNOLOGY, INC. (8000 South Federal Way, Post Office Box 6Boise, Idaho 83707-0006) filed a patent application (PCT/US2025/037346) for "STACKED DIE SEMICONDUCTOR PACKAGE INCLUDING AN ARRAY OF PILLAR STRUCTURES" on Jul 11, 2025. With publication no. WO/2026/024480, the details related to the patent application was published on Jan 29, 2026.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): LEOW, See Hiong (Block 79E, #23-61, Toa Payoh CentralSingapore 315079), NG, Hong Wan (Block 75C, #24-76, Redhill RoadSingapore 153075), CHONG, Chin Hui (Block 10H, #07-29 Braddell HillSinga...