INTERNATIONAL PATENT: MICRON TECHNOLOGY, INC. FILES APPLICATION FOR "MEMORY DIE BONDING IN STACKED SEMICONDUCTOR SYSTEMS"

GENEVA, Feb. 11 -- MICRON TECHNOLOGY, INC. (8000 S. Federal WayBoise, Idaho 83716-9632) filed a patent application (PCT/US2025/039486) for "MEMORY DIE BONDING IN STACKED SEMICONDUCTOR SYSTEMS" on Jul 28, 2025. With publication no. WO/2026/030219, the details related to the patent application was published on Feb 05, 2026.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): HUANG, Sui Chi (8000 S. Federal WayBoise, Idaho 83716-9632), SINGH, Akshay N. (8000 S. Federal WayBoise, Idaho 83716-9632), STREET, Bret K. (8000 S. Federal WayBoise, Idaho 83716-9632)

Abstract: Methods, systems, and devices for me...