INTERNATIONAL PATENT: MICRON TECHNOLOGY, INC. FILES APPLICATION FOR "HYBRID BONDING OF SEMICONDUCTOR CMOS WAFER AND SEMICONDUCTOR MEMORY ARRAY WAFER USING DEBONDABLE CARRIERS"

GENEVA, Jan. 13 -- MICRON TECHNOLOGY, INC. (8000 S. Federal Way, P.O. Box 6Boise, ID 83707-0006) filed a patent application (PCT/US2025/035556) for "HYBRID BONDING OF SEMICONDUCTOR CMOS WAFER AND SEMICONDUCTOR MEMORY ARRAY WAFER USING DEBONDABLE CARRIERS" on Jun 26, 2025. With publication no. WO/2026/010805, the details related to the patent application was published on Jan 08, 2026.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): PAREKH, Kunal, R. (c/o Micron Technology, Inc.8000 S. Federal Way, P.O. Box 6Boise, ID 83707-0006), BAYLESS, Andrew, M. (c/o Micron Technology, Inc.8000 S. Federal Way, ...