INTERNATIONAL PATENT: KYOCERA CORPORATION FILES APPLICATION FOR "PHASE OFFSET REDUCTION BETWEEN BEAM FORMING INTEGRATED CIRCUIT (BFIC) CHANNELS"

GENEVA, April 20 -- KYOCERA CORPORATION (6 Takeda Tobadono-cho, Fushimi-kuKyoto, Kyoto 612-8501) filed a patent application (PCT/US2025/047300) for "PHASE OFFSET REDUCTION BETWEEN BEAM FORMING INTEGRATED CIRCUIT (BFIC) CHANNELS" on Sep 22, 2025. With publication no. WO/2026/080216, the details related to the patent application was published on Apr 16, 2026.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): CARCELLER, Carlos (c/o Kyocera International, Inc. IP Dept.8611 Balboa AvenueSan Diego, California 92123), PAUL, Robert (c/o Kyocera International, Inc. IP Dept.8611 Balboa AvenueSan Diego, Califo...