INTERNATIONAL PATENT: ARTERIS, INC. FILES APPLICATION FOR "GENERATION OF AN OPTIMAL NETWORK-ON-CHIP LAYOUT USING A MACHINE LEARNING MODEL"

GENEVA, April 8 -- ARTERIS, INC. (900 E. Hamilton Avenue, Suite 300Campbell, CA 95008) filed a patent application (PCT/US2025/048872) for "GENERATION OF AN OPTIMAL NETWORK-ON-CHIP LAYOUT USING A MACHINE LEARNING MODEL" on Sep 30, 2025. With publication no. WO/2026/073285, the details related to the patent application was published on Apr 02, 2026.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): JANAC, K., Charles (900 E. Hamilton Avenue, Suite 300Campbell, CA 95008), CHARIF, Amir (900 E. Hamilton AveSuite 300Campbell, CA 95008)

Abstract: An optimal layout of a network-on-chip (NoC) is generated. ...