US Patent Issued on May 12 for "Using a flag to indicate whether a mapping entry points to sequentially stored data" (Idaho Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,625,805, issued on May 12. "Using a flag to indicate whether a mapping entry points to sequentially stored data" was invented by Giuseppe Cariel... Read More

US Patent Issued to Sandisk Technologies on May 12 for "Apparatus and methods for statically mapping random write command data" (Indian Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,625,806, issued on May 12, was assigned to Sandisk Technologies Inc. (Milpitas, Calif.). "Apparatus and methods for statically mapping random wr... Read More

US Patent Issued to Micron Technology on May 12 for "Elastic configuration of data rate control parameters in a memory sub-system with single-level cell memory caching" (American, Indian Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,625,807, issued on May 12, was assigned to Micron Technology Inc. (Boise, Idaho). "Elastic configuration of data rate control parameters in a me... Read More

US Patent Issued to Microsoft Technology Licensing on May 12 for "Cache memory supporting data operations with parametrized latency and throughput" (Washington Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,625,808, issued on May 12, was assigned to Microsoft Technology Licensing LLC (Redmond, Wash.). "Cache memory supporting data operations with pa... Read More

US Patent Issued to Texas Instruments on May 12 for "Cache coherence shared state suppression" (Texas Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,625,809, issued on May 12, was assigned to Texas Instruments Inc. (Dallas). "Cache coherence shared state suppression" was invented by Abhijeet ... Read More

US Patent Issued to Apple on May 12 for "Delayed cache entry invalidation update for potential overwrite re-use" (British, American Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,625,810, issued on May 12, was assigned to Apple Inc. (Cupertino, Calif.). "Delayed cache entry invalidation update for potential overwrite re-u... Read More

US Patent Issued to MICROSOFT TECHNOLOGY LICENSING on May 12 for "Multi-tier memory reclamation" (Indian, American Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,625,811, issued on May 12, was assigned to MICROSOFT TECHNOLOGY LICENSING LLC (Redmond, Wash.). "Multi-tier memory reclamation" was invented by ... Read More

US Patent Issued to SKYECHIP BERHAD on May 12 for "Coherent system and a method of maintaining cache coherence using thereof" (Malaysian Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,625,812, issued on May 12, was assigned to SKYECHIP BERHAD (Bayan Lepas, Malaysia). "Coherent system and a method of maintaining cache coherence... Read More

US Patent Issued to Arm on May 12 for "System level cache with configurable partitioning" (Texas, California Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,625,813, issued on May 12, was assigned to Arm Ltd. (Cambridge, Great Britain). "System level cache with configurable partitioning" was invented... Read More

US Patent Issued to Intel on May 12 for "Graphics processor memory access architecture with address sorting" (American, Indian Inventors)

ALEXANDRIA, Va., May 12 -- United States Patent no. 12,625,814, issued on May 12, was assigned to Intel Corp. (Santa Clara, Calif.). "Graphics processor memory access architecture with address sortin... Read More

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