Intellectual Property India Publishes Patent Application for Thread Tiling For Memory Latency Reduction

MUMBAI, India, July 7 -- Intellectual Property India has published a patent application (202647077498 A) filed by Think Silicon Single Member P. C. on June 23, 2026, for Thread Tiling For Memory Latency Reduction.

Inventors include Bartsokas, Anastasios; Georgakakis, Dimitris; and Keramidas, Georgios.

The application for the patent was published on July 03, 2026, under issue no. 27/2026.

Abstract: A system and method for reducing memory latency utilizing thread tiling. The method includes receiving a tensor input as an array of values, the tensor having a size including a first dimension, a second dimension, and a third dimension; determining an operation type applied to the received tensor input: splitting the received tensor input into...