Intellectual Property India Publishes Patent Application for System And Method For Timing And Power Optimization Of An Integrated Circuit Using Useful Clock Skew And Multi-Threshold-Voltage Cell Optimization

MUMBAI, India, Nov. 2 -- Intellectual Property India has published a patent application (202611110329 A) filed by Ms. Bhavana Bhimineni on September 14, 2026, for System And Method For Timing And Power Optimization Of An Integrated Circuit Using Useful Clock Skew And Multi-Threshold-Voltage Cell Optimization.

Inventor includes Ms. Bhavana Bhimineni.

The application for the patent was published on October 30, 2026, under issue no. 44/2026.

Abstract: A computer-implemented system and method are disclosed for coordinated timing and power optimization of an integrated circuit using useful clock skew and multi- threshold-voltage cell optimization. Design data is analyzed to determine timing-path criticalities, cell sensitivities, clock-endpoi...