MUMBAI, India, Aug. 31 -- Intellectual Property India has published a patent application (202641101328 A) filed by Sr University on August 21, 2026, for Speed And Reliability Analysis Of Single-Exact And Single/Dual Approximate Adders For Next-Generation Approximate Processors.
Inventors include Venne Srilatha; and Padala Sunitha.
The application for the patent was published on August 28, 2026, under issue no. 35/2026.
Abstract: ABSTRACT The present invention relates to a configurable arithmetic architecture for speed and reliability analysis of single-exact, single-approximate, and dual-approximate adders for next-generation approximate processors. The architecture comprises operand input registers, a bit-partitioning unit, an exact add...