Intellectual Property India Publishes Patent Application for Solid-State Electrical Fuse Having A Spatially Programmed Failure Path

MUMBAI, India, Oct. 26 -- Intellectual Property India has published a patent application (202611114831 A) filed by Chandigarh University on September 25, 2026, for Solid-State Electrical Fuse Having A Spatially Programmed Failure Path.

Inventors include Ayush Mahanta; Vaneet Kumar; Payal Mittal; and Neeraj Sharma.

The application for the patent was published on October 23, 2026, under issue no. 43/2026.

Abstract: A solid-state electrical fuse includes first and second electrical terminals connected by a conductive fuse element having spatially separated predefined failure regions. The failure regions differ in at least one physical parameter establishing respective electrical and thermal failure thresholds and collectively defining a spa...