MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202617075630 A) filed by Thales Dis France Sas on June 18, 2026, for Secure Non-Volatile Memory.
Inventors include Naura, David; and Giovinazzi, Thierry.
The application for the patent was published on July 10, 2026, under issue no. 28/2026.
Abstract: The invention relates to a method for detecting a reading error caused by a photoelectric or radiative attack of a non-volatile memory having memory cells (MCj,i) connected to at least one bit line (BLi), and comprising each a floating gate transistor, wherein the reading of a memory cell (MCj,i) is made by pre-charging a bit line (BLi) to a preload voltage and comparison of the bit line voltage to thi...