MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202617075623 A) filed by Thales Dis France Sas on June 18, 2026, for Secure Non-Volatile Memory.
Inventors include Naura, David; and Bour, Laureline.
The application for the patent was published on July 10, 2026, under issue no. 28/2026.
Abstract: The invention relates to a non-volatile memory circuit (300) comprising a plurality of memory cells (MCj,i), a plurality of bit lines (BLi) and a plurality of word lines (WLj to WLj+2), each memory cell (MCj,i) comprising a floating gate transistor (Tfg) for memorizing a bit value and being located at the intersection of a bit line (BLi) and of a word line (WLj), said non-volatile memory circuit (300) comp...