Intellectual Property India Publishes Patent Application for Multi-Stage Error Checking For Polar-Encoded Code Blocks

MUMBAI, India, June 24 -- Intellectual Property India has published a patent application (202617061370 A) filed by Qualcomm Incorporated on May 14, 2026, for Multi-Stage Error Checking For Polar-Encoded Code Blocks.

Inventors include Horn, Idan Michael; Berger, Peer; and Landis, Shay.

The application for the patent was published on June 12, 2026, under issue no. 24/2026.

Abstract: Methods, systems, and devices for wireless communications are described. A network entity may insert one or more error check portions into a polar-encoded signal, where a first error check portion may protect a first portion of the polar-encoded signal. In some examples, a user equipment (UE) may determine a location for the first error check portion based on o...