Intellectual Property India Publishes Patent Application for Direction-Aware Selective Vertical Routing For Port-Constrained 3d Network-On-Chip Architecture

MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202641110675 A) filed by National Institute Of Technology Karnataka on September 15, 2026, for Direction-Aware Selective Vertical Routing For Port-Constrained 3d Network-On-Chip Architecture.

Inventors include Rathnamala Rao; and M. N. Saranya.

The application for the patent was published on September 25, 2026, under issue no. 39/2026.

Abstract: ABSTRACT DIRECTION-AWARE SELECTIVE VERTICAL ROUTING FOR PORT-CONSTRAINED 3D NETWORK-ON-CHIP ARCHITECTURE The present invention relates to direction-aware selective vertical routing system and method, for a port-constrained three-dimensional (3D) Network-on-Chip (NoC) architecture. The system comprises five-...