Intellectual Property India Publishes Patent Application for Counterfactual Error Gap Learning For Latency-Aware Routing In Distributed Ai Inference Systems

MUMBAI, India, Nov. 2 -- Intellectual Property India has published a patent application (202641124641 A) filed by Vellore Institute Of Technology on October 15, 2026, for Counterfactual Error Gap Learning For Latency-Aware Routing In Distributed Ai Inference Systems.

Inventors include A Sivaranjani; and Sajal Varshney.

The application for the patent was published on October 30, 2026, under issue no. 44/2026.

Abstract: ABSTRACT COUNTERFACTUAL ERROR GAP LEARNING FOR LATENCY-AWARE ROUTING IN DISTRIBUTED AI INFERENCE SYSTEMS A latency- aware routing system for distributed artificial intelligence inference includes a gateway router (100) between an edge inference node (114) and a cloud inference node (116), a request feature extractor (102) g...