Intellectual Property India Publishes Patent Application for An Integrated Power-Reduction Framework For Bcd Arithmetic Units Using Multi-Vdd, Clock Gating, And Power Gating

MUMBAI, India, July 7 -- Intellectual Property India has published a patent application (202641078563 A) filed by Sr University on June 25, 2026, for An Integrated Power-Reduction Framework For Bcd Arithmetic Units Using Multi-Vdd, Clock Gating, And Power Gating.

Inventors include Dr. Ts. Narayanamurthy; Dr. Ch. Rajendra Prasad; and Dr. Roseline Oluwaseun Ogundokun.

The application for the patent was published on July 03, 2026, under issue no. 27/2026.

Abstract: AN INTEGRATED POWER-REDUCTION FRAMEWORK FOR BCD ARITHMETIC UNITS USING MULTI-VDD, CLOCK GATING, AND POWER GATING The present invention relates to an integrated power-reduction framework for BCD arithmetic units and VLSI integrated circuits using coordinated multi-VDD, clock gatin...